The present invention relates generally to fabrication of integrated circuit devices and specifically to methods of forming etched via structures used in the fabricated integrated circuit devices.
A common method to etch via/trench structures in low-k intermetal dielectric (IMD) layers or low-k interlevel dielectric (ILD) layers involves forming a patterned photoresist layer over the IMD or IMD layer. A photoresist layer is formed over the structure, the photoresist layer is then selectively exposed and developed to create differing structure portions within the photoresist layer. In a positive photoresist, for example, the exposed, developed portions of the photoresist are then removed to form a patterned photoresist exposing selected portions of the underlying IMD or ILD layers which are then etched.
However the chemical reaction between photoresist and the low-k material occurs and results in footing or scumming at the development step of photolithography.
U.S. Pat. No. 6,025,259 to Yu et al describes a dual damascene process with highly selective boundary layers.
U.S. Pat. No. 6,020,255 to Tsai et al. describes a dual damascene process for borderless interconnects.
U.S. Pat. No. 5,741,626 to Jain et al. describes a dual damascene process with an anti-reflective coating (ARC) layer.
U.S. Pat. No. 6,043,001 to Hirsh et al. describes dual mask pattern transfer techniques in the fabrication of lenslet arrays.
Accordingly, it is an object of the present invention is to provide a method to etch a low-k material via/trench while avoiding a chemical reaction between the photoresist layer and the low-k material.
Another object of the present invention to prevent footing and scumming during photolithography process of low-k via/trench by preventing the chemical reaction between acid of the photoresist layer and the base of the low-k material.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a low-k layer is formed upon the semiconductor structure. A via opening is formed within the low-k layer. An inert polymer liner layer is formed upon the low-k layer and within the via opening. A DUV photoresist layer is formed upon the inert polymer liner layer, filling the inert polymer lined via opening. The inert polymer liner layer preventing adverse chemical reactions between the photoresist layer and portions of the low-k layer. The photoresist layer is patterned to expose the inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening. The exposed inert polymer lined via opening and portions of the inert polymer lined low-k layer adjacent the via opening and the portions of the inert polymer liner layer upon the via opening and portions of the inert polymer lined low-k layer adjacent the via opening are etched to form a structure opening. The patterned photoresist layer is removed. The structure is cleaned and a planarized metal structure is formed within the structure opening.